TSMC is building a PLP mass production system, which can significantly improve the production efficiency of AI chips.

According to a report by etnews on June 15th, TSMC will directly compete with Samsung Electronics using its next-generation semiconductor packaging technology, "Platform-Level Packaging (PLP)." PLP can significantly improve the production efficiency of AI chips, and as TSMC accelerates its preparations for mass production, a leadership battle between it and Samsung Electronics, which entered the market first, seems inevitable. Industry sources revealed on the 15th that TSMC is building its Materials, Components, and Equipment (MCE) supply chain to establish its PLP mass production system. Currently, TSMC is discussing equipment investment with domestic and international MCE companies. Reportedly, TSMC plans to begin PLP mass production as early as next year, a move seen as a substantial step towards this goal. PLP is a technology that cuts a completed circuit-manufacturing wafer into individual chips (dies), which are then packaged on rectangular panels to produce finished products. This contrasts with "Wafer-Level Packaging (WLP)," which is performed on circular wafers. When packaging chips on circular wafers, the edge areas cannot be made into chips and must be discarded—meaning lower productivity. Packaging on rectangular panels allows for waste-free chip production. Using a standard 600×600 mm rectangular panel, approximately five to six times more chips can be produced compared to the mainstream 300 mm (12-inch) wafer. Currently, Samsung Electronics holds an advantage in PLP technology. After acquiring the PLP business from Samsung Electro-Mechanics in 2019, Samsung Electronics has continuously accumulated technological capabilities by applying the technology to mobile application processors (APs) and power management ICs (PMICs). In contrast, TSMC has previously been relatively passive in PLP, as it has established a competitive advantage in the foundry field through traditional wafer-level packaging (WLP). However, with the explosive growth of the AI chip market, the situation has reversed—PLP can increase the output of AI chips and facilitate the realization of large-area AI chips. Therefore, TSMC has been actively promoting its PLP business since 2024. TSMC is expected to build and operate a pilot production line this year, and after performance evaluation, enter mass production around next year. TSMC has reportedly secured a global AI chip customer. As TSMC accelerates PLP mass production, competition with Samsung Electronics is expected to intensify. Samsung also plans to expand the application of PLP from existing APs and PMICs to high-performance computing (HPC) chips, such as AI semiconductors. Furthermore, glass substrates, which have garnered significant attention as AI chip substrates, are also likely to be used in this PLP process—indicating a leadership battle between Samsung Electronics and TSMC in the next-generation substrate market. An industry insider stated, "Not only Samsung Electronics and TSMC, but also a large number of global OSAT (Outsourced Semiconductor Assembly and Test) companies have entered the PLP process market," adding, "Intense competition is expected, but the market will also grow."