Analysts: HBM packaging route changes; SPHBM4 may push the bottleneck of AI chips to the underlying chip.

According to Mars Finance, on June 23, analyst Damnang stated in an article published on June 22 that JEDEC's newly released SPHBM4 standard does not make DRAM itself faster, larger, or cheaper, but rather changes the way HBMs connect to GPUs. Traditional HBM4 requires a silicon interposer to connect to the GPU, while SPHBM4 attempts to allow HBMs to bypass the silicon interposer and connect directly to the organic packaging substrate. The core technology of SPHBM4 is to reuse the DRAM stack of HBM4, only redesigning the bottom base die. Traditional HBM4 has 2048 data signal pins and must rely on a silicon interposer to handle extremely dense connection spacing; SPHBM4 reduces the number of pins to 512 and increases the speed of a single pin by four times through 4:1 serialization, thus theoretically maintaining a total bandwidth close to that of HBM4. Damnang believes that the key to this standard is not "cheaper HBMs," but rather releasing advanced packaging capacity. While HBMs are expensive and scarce, silicon interposers and CoWoS (CoWall-on-Semiconductor) are also significant bottlenecks in AI accelerator shipments. If HBMs no longer occupy interposer area, the same interposer wafer capacity could potentially support more package shipments. The article estimates that in high-end AI accelerators, HBMs may occupy close to half of the silicon interposer area. If this area were removed, the number of packages that a single wafer could theoretically support could increase by 1.5 to 2 times. However, the actual effect still depends on adoption rate, yield, product configuration, and the remaining interposer area on the GPU side. Therefore, SPHBM4 truly releases capacity, not per-chip cost. Even if similar technologies can save 22% to 40% on packaging costs, this is only a single-digit percentage in the total cost of the entire AI accelerator. More important than saving hundreds of dollars per chip is the potential increase in GPU and ASIC production after the shipment bottleneck is removed. The beneficiaries may not be immediately apparent. In the short term, even if a cloud vendor or chip company adopts SPHBM4 first, the released CoWoS capacity may be redistributed by TSMC to its queuing customers, while Nvidia may still be best positioned to absorb the new capacity. For cloud vendors developing their own ASICs, the value of SPHBM4 is more long-term: reducing reliance on large-area silicon interposers and increasing design and shipping freedom. The value chain will also shift accordingly. Damnang stated that SPHBM4 will shift the technological burden from substrates and silicon interposers to high-speed logic design on the base die. Because with increased single-pin speed, PHY, SerDes, clock recovery, equalization, and error correction circuits will become more important. The focus of HBM competition may shift from "who can stack the highest" to "who can make the underlying logic better." At the company level, Samsung possesses a vertically integrated advantage due to its simultaneous capabilities in memory, advanced logic processes, and packaging. SK Hynix and Micron rely more on TSMC's advanced nodes to achieve complex base dies. Even with the shrinking interposer area, TSMC still controls CoWoS and base die manufacturing. Intel, with its EMIB, high-speed interconnect, and advanced packaging capabilities, is a potential variable. However, SPHBM4 is currently still in the "standard release, awaiting adoption" stage. Three things need to be observed next: which memory manufacturer will launch SPHBM4 products first, whether large cloud vendors will incorporate this design into their self-developed ASICs, and whether JEDEC will disclose complete technical details. Damnang is an analyst who has long focused on semiconductor and AI infrastructure. His Substack primarily publishes analyses of the semiconductor, memory, advanced packaging, foundry, and AI chip supply chains, characterized by breaking down complex engineering problems into industry logic that investors can understand.